Configurable Logic Block

A single sram cell

The first building block in a CLB is an SRAM. 

The SRAM cell was designed to incorporate both read and write functionalities. During a write operation, the write circuitry is engaged when the write enable is active. Subsequently, the bit line is dynamically driven to the specified value. In the read operation, the bit line undergoes precharging for half of the clock period. Depending on the stored value, the bit line either remains at VDD or is discharged back to GND. We chose a 6T-SRAM design due to its simplicity. When designing the SRAM, we had to experiment with the sizing of the NMOS widths (N0 and N3) and pass transistor (N1 and N2) widths. 

This 6T SRAM cell has both read and write capabilities. This is determined by the EN (Write ENable pin). When it is high, the BL is written to the value on DATA. To read, the BL is pre charged and then switches to the stored value.

To complete the SRAM functionality, we added more transistor logic and found that in order to be reliable, the NMOS transistors associated with the writing circuitry needed to be much larger than the PMOS to ensure that even when the PMOS is on, the BL and BL’ can still be pulled down.

building and testing the clb

To build and test the CLB, we created many components in Cadence including the SRAM, Multiplexer, Clock, D-Flip-Flop, and countless testing setups.

Our design goal was to minimize the area of the CLB as much as we could, while still maintaining reliability. The CLB has inputs for the Clock, Load, 16 bit data, and LUT select and only one output. Below is the final CLB schematic.